A memory chip generally comprises a plurality of memory cells that are deposited onto a silicon wafer and addressable via an array of column conducting leads (bit lines) and row conducting leads (word lines). That is, the intersection of a bit line and a word line typically constitutes the address of a memory cell. The memory cells are controlled by specialized circuits that perform functions such as identifying rows and columns from which data are read from or to which data are written. Typically, each memory cell stores data in the form of a “1” or a “0,” representing a bit of data.
An array of magnetic memory cells is often called magnetic random access memory or MRAM. MRAM is generally nonvolatile memory (i.e., a solid state chip that retains data when power is turned off). At least one type of magnetic memory cell includes a data layer and a reference layer, separated from each other by at least one intermediate layer. The data layer may also be referred to as a bit layer, a storage layer, a sense layer, and/or using other known terminology. In a magnetic memory cell, a bit of data (e.g., a “1” or “0”) may be stored by “writing” into the data layer via one or more conducting leads (e.g., a bit line and a word line). The write operation is typically accomplished via a write current that sets the orientation of the magnetic moment in the data layer to a predetermined direction.
Once written, the stored bit of data may be read by providing a read current through one or more conducting leads (e.g., a read line) to the magnetic memory cell. For each memory cell, the orientations of the magnetic moments of the data layer and the reference layer are either parallel (in the same direction) or anti-parallel (in different directions) to each other. The degree of parallelism affects the resistance of the cell, and this resistance can be determined by sensing (e.g., via a sense amplifier) an output current or voltage produced by the memory cell in response to the read current.
More specifically, if the magnetic moments are parallel, the resistance determined based on the output current is of a first relative value (e.g., relatively low). If the magnetic moments are anti-parallel, the resistance determined is of a second relative value (e.g., relatively high). The relative values of the two states (i.e., parallel and anti-parallel) are typically different enough to be sensed distinctly. A “1” or a “0” may be assigned to the respective relative resistance values depending on design specification.
The intermediate layer, which may also be referred to as a spacer layer, may comprise insulating material (e.g., dielectric), non-magnetic conducting material, and/or other known materials, and is usually thick enough to prevent exchange coupling between the data and reference layers. The various conducting leads which are used to address the memory cells (e.g., bit lines, word lines, and read lines), and to provide currents to pass through the data and reference layers to read data from or write data to the memory cells are provided by one or more additional layers, called conducting layer(s).
The layers described above and their respective characteristics are typical of magnetic memory cells based on tunneling magnetoresistance (TMR) effects known in the art. Other combinations of layers and characteristics may also be used to make magnetic memory cells based on TMR effects. For example, a pinned reference layer and an anti-ferromagnetic layer may also be used. This configuration of TMR memory cells is well known in the art and need not be described in more detail herein. See, for example, U.S. Pat. No. 6,404,674, issued to Anthony et al., and co-pending U.S. application Nos.: (1) Ser. No. 09/825,093, entitled “Cladded Read Conductor For A Pinned-On-The-Fly Soft Reference Layer”, filed on Apr. 2, 2001; and (2) Ser. No. 09/963,171, entitled “Magneto-Resistive Device Having Soft Reference Layer”, filed on Sep. 25, 2001, which are hereby incorporated by reference in their entirety for all purposes.
Still other configurations of magnetic memory cells based on other well known physical effects (e.g., giant magnetoresistance (GMR), anisotropic magnetoresistance (AMR), colossal magnetoresistance (CMR), and/or other physical effects) may be implemented with various embodiments described herein.
Throughout this application, various exemplary embodiments will be described in reference to the TMR memory cells as described above. Those skilled in the art will readily appreciate that the exemplary embodiments may also be implemented with other types of magnetic memory cells known in the art (e.g., other types of TMR memory cells, GMR memory cells, AMR memory cells, CMR memory cells, etc.) according to the requirements of a particular implementation.
Generally speaking, desirable characteristics for any configuration of memory device include increased speed, reduced power consumption, and/or lower cost. A simpler fabrication process and/or a smaller chip size may achieve lower cost. However, as magnetic memory cells become smaller, typically, higher operating current is required for achieving “write” operations. Magnetic coercivity increases as memory cell area decreases. As a result, an increased write current is generally needed to reverse the polarity of one or more layers of the memory cell. Higher operating current is undesirable because it goes hand-in-hand with higher power requirements, increased concern about electromigration, increased write circuitry area, and increased cost.
Thus, a market exists for improved memory cell configurations that can be manufactured by a simpler fabrication process and/or use lowered operating current in high density MRAM devices.